Marvell Structera X 3406 and 3506 CXL 3.2 Expanders Target AI Memory Wall

Marvell's introduction of the Structera X 3406 and 3506 marks a significant generational step forward for Compute Express Link (CXL) hardware, shifting from four-channel architectures to a robust six-channel design. Built on a 5nm process, the 3406 model handles up to 18 DDR4 RDIMMs for a maximum of 9TB of capacity, while the 3506 variant accommodates up to 12 DDR5 RDIMMs delivering up to 6TB. Both controllers leverage PCIe Gen 6.0 x16 host connectivity to deliver up to 256 GB/s of bandwidth across up to four independent host systems.

For enterprise hardware teams architecting servers for AI inference and large language model (LLM) serving, the integration of hardware-accelerated inline LZ4 compression is a critical feature. Marvell reports that the compression engine matches the line rate to effectively double or triple physical DRAM capacity depending on the workload, helping mitigate the server memory wall. Furthermore, the devices incorporate advanced security architectures, including CXL IDE, AES-256 memory encryption, and Caliptra 2.0 post-quantum cryptographic support.

Hardware designers and enterprise buyers should note that these second-generation expanders are slated to begin sampling in Q1 2027, following initial demonstrations at the OCP Global Summit. Early validation partnerships are already underway with major memory suppliers like Samsung and SK hynix, alongside ecosystem support from compute vendors such as AMD and Arm. Server architecture roadmaps targeting high-density multi-host memory pooling should evaluate how CXL 3.2 infrastructure aligns with upcoming PCIe Gen 6 platform rollouts.