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74AUP1G86GW,125 AI Analysis:
Datasheet, Specs, Alternatives & ECAD

AI summary

74AUP1G86GW,125 product

74AUP1G86GW,125

Logic

XOR GateLow PowerLogic IC

The 74AUP1G86 is a low-power, single 2-input XOR gate designed for wide-voltage operation (0.8 V to 3.6 V) with integrated Schmitt-trigger inputs.

Best for

  • Battery-powered applications
  • Low-voltage logic systems

Avoid if

  • High-speed requirements exceeding 4 ns propagation delay

Check before use

  • Input voltage levels relative to VCC

Key specifications

Supply Voltage
0.8 V - 3.6 V
Propagation Delay
4.0 ns (3.3 V, 5 pF)
Quiescent Current
0.9 μA (max)

Compliance & Environment

RoHS
ROHS3 Compliant
REACH
REACH Unaffected
MSL
1 (Unlimited)
ECCN
EAR99
HTSUS
8542.39.0001

Application

General Logic

Datasheet

NXP-Semiconductors-company-13.pdf

800 KB

Datasheet AI

CAD Models

Download ECAD models for 74AUP1G86GW,125: KiCad symbol & footprint, Altium footprint, PCB footprint, and 3D model.

EDA Symbol
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PCB Footprint
Land pattern for PCB layout
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3D Model
STEP file for mechanical design
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Verified KiCad 8 symbol, footprint, and 3D model
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Where to Buy

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Alternative components

Alternatives are being enriched. Analyze this part in PartGenie for the latest matches.

Design and risk insights

Questions & answers

It is a single 2-input EXCLUSIVE-OR gate from Nexperia's AUP (Advanced Ultra-low Power) logic family.