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74HC112PW,118 AI Analysis:
Datasheet, Specs, Alternatives & ECAD

AI summary

74HC112PW,118 product

74HC112PW,118

Flip Flops

Flip-FlopJKLogic

The 74HC112PW,118 is a dual negative-edge triggered JK flip-flop from Nexperia, housed in a TSSOP-16 package.

Best for

  • General logic circuits
  • State machines

Avoid if

  • Applications requiring TTL input levels (use 74HCT series instead)

Check before use

  • Timing constraints for J, K, and clock inputs

Key specifications

Logic Family
74HC
Trigger
Negative Edge
Voltage
2V - 6V

Compliance & Environment

RoHS
Compliant
REACH
-
MSL
-
ECCN
-
HTSUS
-

Application

General Logic

Datasheet

sf-00079955.pdf

800 KB

Datasheet AI

CAD Models

Download ECAD models for 74HC112PW,118: KiCad symbol & footprint, Altium footprint, PCB footprint, and 3D model.

EDA Symbol
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PCB Footprint
Land pattern for PCB layout
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3D Model
STEP file for mechanical design
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Where to Buy

Real-time and catalog pricing from verified distributors

Live prices updated on demand · Catalog (~) prices may differ

Alternative components

Alternatives are being enriched. Analyze this part in PartGenie for the latest matches.

Design and risk insights

Questions & answers

It is a dual JK flip-flop with asynchronous set and reset inputs, designed for high-speed CMOS logic applications.