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74HC138PW,118 AI Analysis:
Datasheet, Specs, Alternatives & ECAD

AI summary

74HC138PW,118 product

74HC138PW,118

Programmers

DecoderDemultiplexerLogic ICNexperia

The 74HC138PW,118 is a high-speed CMOS 3-to-8 line decoder/demultiplexer from Nexperia, designed for memory chip select decoding and general logic applications.

Best for

  • Memory address decoding
  • Signal demultiplexing
  • General logic expansion

Avoid if

  • Applications requiring TTL-level inputs (use 74HCT138 instead)

Check before use

  • Input voltage levels
  • Propagation delay timing

Key specifications

Supply Voltage
2.0 V to 6.0 V
Logic Family
74HC
Package
16-TSSOP
Operating Temp
-40 °C to +125 °C

Compliance & Environment

RoHS
ROHS3 Compliant
REACH
REACH Unaffected
MSL
1 (Unlimited)
ECCN
EAR99
HTSUS
8542.39.0001

Application

IndustrialGeneral Logic

Datasheet

NXP-Semiconductors-company-13.pdf

800 KB

Datasheet AI

CAD Models

Download ECAD models for 74HC138PW,118: KiCad symbol & footprint, Altium footprint, PCB footprint, and 3D model.

EDA Symbol
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PCB Footprint
Land pattern for PCB layout
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3D Model
STEP file for mechanical design
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Where to Buy

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Alternative components

Alternatives are being enriched. Analyze this part in PartGenie for the latest matches.

Design and risk insights

Questions & answers

It is a 3-to-8 line decoder/demultiplexer that converts three binary address inputs into eight mutually exclusive outputs.