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74HC73PW,118 AI Analysis:
Datasheet, Specs, Alternatives & ECAD

AI summary

74HC73PW,118 product

74HC73PW,118

Interface

Logic ICFlip-FlopNexperia

The 74HC73PW,118 is a dual JK flip-flop with asynchronous reset, designed for high-speed logic applications requiring negative-edge triggering.

Best for

  • General logic circuits
  • Sequential logic design

Avoid if

  • Applications requiring positive-edge triggering

Check before use

  • Clock signal rise/fall times

Key specifications

Supply Voltage
2.0 V - 6.0 V
Trigger
Negative Edge

Compliance & Environment

RoHS
ROHS3 Compliant
REACH
REACH Unaffected
MSL
1 (Unlimited)
ECCN
EAR99
HTSUS
8542.39.0001

Application

General Logic

Datasheet

NXP-Semiconductors-company-13.pdf

800 KB

Datasheet AI

CAD Models

Download ECAD models for 74HC73PW,118: KiCad symbol & footprint, Altium footprint, PCB footprint, and 3D model.

EDA Symbol
Schematic symbol for your EDA tool
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PCB Footprint
Land pattern for PCB layout
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3D Model
STEP file for mechanical design
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KiCad Library
Verified KiCad 8 symbol, footprint, and 3D model
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Where to Buy

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Live prices updated on demand · Catalog (~) prices may differ

Alternative components

Alternatives are being enriched. Analyze this part in PartGenie for the latest matches.

Design and risk insights

Questions & answers

It is a dual JK flip-flop with individual J, K, clock, and reset inputs, featuring negative-edge triggering.