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74LVC573APW,118 AI Analysis:
Datasheet, Specs, Alternatives & ECAD

AI summary

74LVC573APW,118 product

74LVC573APW,118

Interface

LogicLatchOctal

The 74LVC573A is an 8-bit D-type transparent latch with 3-state outputs, optimized for 1.2 V to 3.6 V supply voltages and 5 V tolerant I/O.

Best for

  • Data bus buffering
  • Mixed-voltage level translation

Avoid if

  • Applications requiring non-transparent latching

Check before use

  • Timing requirements for LE and OE signals

Key specifications

Supply Voltage
1.2 V to 3.6 V
Logic Type
D-Type Transparent Latch
Output Type
3-State

Compliance & Environment

RoHS
ROHS3 Compliant
REACH
REACH Unaffected
MSL
1 (Unlimited)
ECCN
EAR99
HTSUS
8542.39.0001

Application

General Logic

Datasheet

NXP-Semiconductors-company-13.pdf

800 KB

Datasheet AI

CAD Models

Download ECAD models for 74LVC573APW,118: KiCad symbol & footprint, Altium footprint, PCB footprint, and 3D model.

EDA Symbol
Schematic symbol for your EDA tool
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PCB Footprint
Land pattern for PCB layout
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3D Model
STEP file for mechanical design
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KiCad Library
Verified KiCad 8 symbol, footprint, and 3D model
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Where to Buy

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Alternative components

Alternatives are being enriched. Analyze this part in PartGenie for the latest matches.

Design and risk insights

Questions & answers

It is an octal D-type transparent latch with 3-state outputs, designed for high-speed CMOS applications.