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CD74HC112PWR AI Analysis:
Datasheet, Specs, Alternatives & ECAD

AI summary

CD74HC112PWR product

CD74HC112PWR

Flip Flops

Flip-FlopCMOSLogic

The CD74HC112PWR is a dual J-K flip-flop in a 16-pin TSSOP package, suitable for high-speed CMOS logic applications.

Best for

  • General logic circuits
  • State machine design

Avoid if

  • Applications requiring TTL-level inputs (use HCT series instead)

Check before use

  • Input voltage levels and timing constraints

Key specifications

Logic Family
HC
Trigger
Negative Edge
Package
TSSOP-16

Compliance & Environment

RoHS
ROHS3 Compliant
REACH
-
MSL
Level-1-260C-UNLIM
ECCN
-
HTSUS
-

Application

General Logic

Datasheet

GESOS01215-1.pdf

800 KB

Datasheet AI

CAD Models

Download ECAD models for CD74HC112PWR: KiCad symbol & footprint, Altium footprint, PCB footprint, and 3D model.

EDA Symbol
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PCB Footprint
Land pattern for PCB layout
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3D Model
STEP file for mechanical design
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Where to Buy

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Alternative components

Alternatives are being enriched. Analyze this part in PartGenie for the latest matches.

Design and risk insights

Questions & answers

It is a dual negative-edge-triggered J-K flip-flop with asynchronous set and reset capabilities, designed for high-speed CMOS logic applications.