ISO6760LDWR AI Analysis:
Datasheet, Specs, Alternatives & ECAD

It is intended for isolated CMOS or LVCMOS control lines, particularly three-phase motor drives and intelligent power modules where paired high-side and low-side commands must not be active simultaneously.

Review the interlock truth table, because a high level on both inputs in one pair produces low outputs. Also verify the required data rate at the selected supply voltage, output loading, startup behavior, isolation rating, and board creepage and clearance.

Key specifications include six forward channels with three interlock pairs, non-inverting outputs, up to 50 Mbps at 2.25 V to 5.5 V, 5000 VRMS UL 1577 isolation, 1500 VRMS working isolation, and -40 °C to 125 °C operation.

Use the ISO6760LDWR datasheet for the official pinout diagram and pin names. In PartGenie, ask Datasheet AI about ISO6760LDWR pinout to locate pins, power rails, and interface signals before layout.