LMUN5314DW1T1G Datasheet, Specs, Alternatives & ECAD | LRC | PartGenie

AI summary

LMUN5314DW1T1G product

The LMUN5314DW1T1G is a dual NPN/PNP pre-biased transistor in a SOT-363 package, designed to replace discrete components with an integrated resistor network.

Best for

Space-constrained switching applications
Signal conditioning

Avoid if

High-power applications exceeding 100mA

Check before use

Thermal dissipation limits when both junctions are active

Key specifications

VCEO: 50 V
IC: 100 mA
R1/R2: 10k/47k

Compliance & Environment

RoHS: Yes
REACH: -
MSL: -
ECCN: -
HTSUS: -

Application

General SwitchingIndustrial Control

Datasheet

279495d349d314933de0da3b1e096c97.pdf

800 KB

CAD Models

Download ECAD models for LMUN5314DW1T1G: KiCad symbol & footprint, Altium footprint, PCB footprint, and 3D model.

EDA Symbol

Schematic symbol for your EDA tool

PCB Footprint

Land pattern for PCB layout

3D Model

STEP file for mechanical design

KiCad Library

Verified KiCad 8 symbol, footprint, and 3D model

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Alternative components

Alternatives are being enriched. Analyze this part in PartGenie for the latest matches.

Design and risk insights

Questions & answers

It is a dual-transistor device (one NPN, one PNP) featuring integrated bias resistors, housed in a compact SOT-363 surface-mount package.