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PDTC114TU,115 AI Analysis:
Datasheet, Specs, Alternatives & ECAD

AI summary

PDTC114TU,115 product

PDTC114TU,115

Power Management (PMIC)

NPNPre-BiasedSOT323

The PDTC114TU is an NPN resistor-equipped transistor (RET) featuring a 10 kΩ input bias resistor, designed for space-saving digital switching and IC input control.

Best for

  • Digital switching
  • IC input interfacing

Avoid if

  • High-power applications exceeding 200 mW

Check before use

  • Thermal dissipation in high-density layouts

Key specifications

Type
NPN Pre-Biased
R1
10 kΩ
VCEO
50 V
IC Max
100 mA

Compliance & Environment

RoHS
ROHS3 Compliant
REACH
REACH Unaffected
MSL
1 (Unlimited)
ECCN
EAR99
HTSUS
8541.21.0095

Application

Digital LogicIC Interfacing

Datasheet

NXP-Semiconductors-company-13.pdf

800 KB

Datasheet AI

CAD Models

Download ECAD models for PDTC114TU,115: KiCad symbol & footprint, Altium footprint, PCB footprint, and 3D model.

EDA Symbol
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PCB Footprint
Land pattern for PCB layout
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3D Model
STEP file for mechanical design
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Alternative components

Alternatives are being enriched. Analyze this part in PartGenie for the latest matches.

Design and risk insights

Questions & answers

It is an NPN transistor with integrated bias resistors (R1=10kΩ), designed to reduce component count in digital circuits.