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PUDP-10V-S AI Analysis:
Datasheet, Specs, Alternatives & ECAD

AI summary

PUDP-10V-S product

PUDP-10V-S

Interconnects

JSTPUD SeriesCrimp Housing2.0mm Pitch

The PUDP-10V-S is a 10-position, 2.0mm pitch double-row crimp housing from JST's PUD series, designed for secure board-to-wire connections.

Best for

  • Compact board-to-wire applications
  • Vibration-prone environments

Avoid if

  • High-power applications exceeding 3A
  • Environments exceeding 85°C

Check before use

  • Ensure correct crimp terminal selection
  • Verify mating header compatibility

Key specifications

Pitch
2.0 mm
Positions
10
Current Rating
3 A

Compliance & Environment

RoHS
Compliant
REACH
-
MSL
-
ECCN
-
HTSUS
-

Application

IndustrialConsumer Electronics

Datasheet

PUDP-10V-S-JST-datasheet-12395095.pdf

800 KB

Datasheet AI

CAD Models

Download ECAD models for PUDP-10V-S: KiCad symbol & footprint, Altium footprint, PCB footprint, and 3D model.

EDA Symbol
Schematic symbol for your EDA tool
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PCB Footprint
Land pattern for PCB layout
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3D Model
STEP file for mechanical design
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KiCad Library
Verified KiCad 8 symbol, footprint, and 3D model
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Where to Buy

Real-time and catalog pricing from verified distributors

Live prices updated on demand · Catalog (~) prices may differ

Alternative components

Alternatives are being enriched. Analyze this part in PartGenie for the latest matches.

Design and risk insights

Questions & answers

It is a 10-position (2x5) receptacle housing for the JST PUD connector series, featuring a 2.0mm pitch and a secure locking mechanism.