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PUMD16,115 AI Analysis:
Datasheet, Specs, Alternatives & ECAD

AI summary

PUMD16,115 product

PUMD16,115

Power Management (PMIC)

Dual TransistorPre-biasedNPN/PNPSOT363

The PUMD16 is a dual NPN/PNP pre-biased transistor array featuring integrated bias resistors, designed for space-saving digital switching and driver applications.

Best for

  • Digital circuit switching
  • Peripheral driver circuits
  • IC input control

Avoid if

  • High-power switching applications exceeding 300mW

Check before use

  • Input voltage polarity and maximum current ratings

Key specifications

Configuration
1 NPN, 1 PNP
R1 / R2
22kΩ / 47kΩ
VCEO
50V
Package
SOT363 (SC-88)

Compliance & Environment

RoHS
ROHS3 Compliant
REACH
REACH Unaffected
MSL
1 (Unlimited)
ECCN
EAR99
HTSUS
8541.21.0095

Application

GeneralIndustrial

Datasheet

NXP-Semiconductors-company-13.pdf

800 KB

Datasheet AI

CAD Models

Download ECAD models for PUMD16,115: KiCad symbol & footprint, Altium footprint, PCB footprint, and 3D model.

EDA Symbol
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PCB Footprint
Land pattern for PCB layout
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3D Model
STEP file for mechanical design
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Where to Buy

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Alternative components

Alternatives are being enriched. Analyze this part in PartGenie for the latest matches.

Design and risk insights

Questions & answers

The PUMD16 is a resistor-equipped transistor (RET) array containing one NPN and one PNP transistor, each with integrated bias resistors (R1=22kΩ, R2=47kΩ).