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PUMD9,115 AI Analysis:
Datasheet, Specs, Alternatives & ECAD

AI summary

PUMD9,115 product

PUMD9,115

Power Management (PMIC)

Pre-biasedDual TransistorSOT363

The PUMD9 is a dual NPN/PNP pre-biased transistor in a compact SOT363 package, designed for space-saving digital switching and IC input control.

Best for

  • Digital switching
  • IC input control
  • Automotive and industrial digital segments

Avoid if

  • High-power applications exceeding 300mW total dissipation

Check before use

  • Thermal derating curve for ambient temperatures above 25°C

Key specifications

Configuration
1 NPN, 1 PNP (Dual)
R1 / R2
10kΩ / 47kΩ
Max VCEO
50V

Compliance & Environment

RoHS
ROHS3 Compliant
REACH
REACH Unaffected
MSL
1 (Unlimited)
ECCN
EAR99
HTSUS
8541.21.0095

Application

Digital SwitchingIC Input Control

Datasheet

NXP-Semiconductors-company-13.pdf

800 KB

Datasheet AI

CAD Models

Download ECAD models for PUMD9,115: KiCad symbol & footprint, Altium footprint, PCB footprint, and 3D model.

EDA Symbol
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PCB Footprint
Land pattern for PCB layout
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3D Model
STEP file for mechanical design
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Where to Buy

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Live prices updated on demand · Catalog (~) prices may differ

Alternative components

Alternatives are being enriched. Analyze this part in PartGenie for the latest matches.

Design and risk insights

Questions & answers

The PUMD9 is a resistor-equipped double transistor (RET) containing one NPN and one PNP transistor, each with integrated bias resistors.