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SN74AUP1G125DCKR(UMW) AI Analysis:
Datasheet, Specs, Alternatives & ECAD

AI summary

SN74AUP1G125DCKR(UMW) product

SN74AUP1G125DCKR(UMW)

Buffers

LogicBufferULP

The SN74AUP1G125 is a low-power, single-buffer gate with 3-state output, suitable for 0.8V to 3.6V logic applications.

Best for

  • Battery-powered devices
  • Low-voltage logic level shifting

Avoid if

  • High-current drive applications

Check before use

  • Moisture sensitivity level (MSL 3)

Key specifications

VCC Range
0.8V - 3.6V
Max ICC
0.7 µA
Package
SC70-5

Compliance & Environment

RoHS
Compliant
REACH
-
MSL
3
ECCN
-
HTSUS
-

Application

General Logic

Datasheet

15526e7aa85806e2dfbb235aee16312f_2405091436_UMW-Youtai-Semiconductor-Co---Ltd--SN74AUP1G125DCKR-UMW_C22396375.pdf

800 KB

Datasheet AI

CAD Models

Download ECAD models for SN74AUP1G125DCKR(UMW): KiCad symbol & footprint, Altium footprint, PCB footprint, and 3D model.

EDA Symbol
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PCB Footprint
Land pattern for PCB layout
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3D Model
STEP file for mechanical design
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Alternative components

Alternatives are being enriched. Analyze this part in PartGenie for the latest matches.

Design and risk insights

Questions & answers

It is a single-buffer gate with a 3-state output from the ultra-low power (ULP) series, designed for high-speed operation in low-voltage systems.