TPRLST23A712C Datasheet, Specs, Alternatives & ECAD | TECH PUBLIC | PartGenie

AI summary

TPRLST23A712C product

TPRLST23A712C is a SOT-23 dual-path asymmetrical TVS array for protecting separate 12 V and 7 V lines against ESD and transient pulses.

Best for

Dual-line 7 V and 12 V transient protection
ESD protection at external interfaces
Space-constrained SOT-23 designs

Avoid if

Both lines require the same protection voltage
The protected circuit cannot tolerate the specified clamping voltage
Package pinout cannot route pin 3 directly to ground

Check before use

Confirm pin 1 and pin 2 line assignments
Check 75 pF maximum junction capacitance against signal loading
Review transient waveform and thermal derating for the application

Key specifications

Peak pulse power: 200 W (8/20 us)
Peak pulse current: 8 A (8/20 us)
Working voltage: 12 V and 7 V paths
ESD rating: +/-30 kV, IEC 61000-4-2
Package: SOT-23, 3 pins

Compliance & Environment

RoHS: Compliant
REACH: -
MSL: Level 3 per J-STD-020
ECCN: -
HTSUS: -

Application

RS485 portsNetwork interfacesPortable instrumentationWireless systems

Datasheet

26b54603dfa3049bfb2e1bf12cd45a8f_TPRLST23A712C.pdf

800 KB

CAD Models

Download ECAD models for TPRLST23A712C: KiCad symbol & footprint, Altium footprint, PCB footprint, and 3D model.

EDA Symbol

Schematic symbol for your EDA tool

PCB Footprint

Land pattern for PCB layout

3D Model

STEP file for mechanical design

KiCad Library

Verified KiCad 8 symbol, footprint, and 3D model

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Alternative components

Alternatives are being enriched. Analyze this part in PartGenie for the latest matches.

Design and risk insights

Questions & answers

It is a 3-pin SOT-23 asymmetrical TVS diode array. Pins 1 and 2 each have a dedicated protection path to pin 3, which is ground.